Such a method is known from U.S. Pat. No. 5,963,841. According to this method conductive gates are formed in a semiconductor device through the use of a “bottom anti-reflective coating” (BARC). The starting material is the substrate provided with a dielectric layer, a conductive layer, e.g. of polycrystalline silicon, a BARC layer provided with an oxide layer, and a resist mask. The regions of the oxide layer selected by the resist mask, the BARC, and the conductive layer are etched. Then the resist mask is removed so that the subjacent oxide layer becomes exposed. The oxide layer is then removed using a conventional wet etching technique and HF (hydrofluoric acid) solution, which exposes the BARC. Finally, the remaining BARC is removed using a conventional wet etching technique and H3PO4 (phosphoric acid) solution.
It was found in the known method that a loss of the critical dimension (CD) of the gate occurs. The dimension of the passage in the conductive layer does not correspond exactly anymore to the dimension defined by the resist mask. A good CD control is of a major importance in view of the continuing trend towards decreased dimensions of devices within an integrated circuit.